1. Field of Endeavor
The teachings in accordance with exemplary and non-limiting embodiments of this disclosure relate generally to a circuit for memory sharing, and more particularly to a circuit for memory sharing configured to share data among processors of an electronic circuit in an IED (Intelligent Electronic Device) used as a controller for protection/control of an electrical power system.
2. Background
This section provides background information related to the present disclosure which is not necessarily prior art.
An IED (Intelligent Electronic Device) used as a controller for protection/control of an electrical power system is largely embedded with dedicated numeric data processors, or two or more dedicated processors for high speed communication designed to support the IEC61850 standard. Each processor performs operation, control and main processor functions. The IED must be able to perform production and process of massive data such as accident history caused by system accident or control and waveform storage and generation of system at a high speed within 1 msec or at a similar high speed, and the data must be shared among each processor.
To this end, a dual port memory supplied by a conventional memory manufacturer may be used, but usage of dual port memory to an IED system poses several problems.
First, capacity of dual port memory supplied by memory manufacturer is generally limited several hundred Kbytes. An IED used for electric power system requires capacity of massive memory data because it must be shared with several processors for communication, operation and main processing of data of accident waveform information, but most of the commercialized dual port memories cannot be used due to limit in capacity.
Another problem is that the conventionally marketed dual port memory is not a battery backed-up low power memory and therefore is not suitable for an IED that requires data backup through a battery or a super capacitor. Still another problem is that the commercialized dual port memory uses a high-priced IC twice the price of a conventional SRAM.
Hence, there is a need to develop a memory sharing circuit using a general memory.